1. Field of the Invention
This invention relates to microprocessors and, more particularly, to methods and apparatus for increasing the speed of microprocessors.
2. History of the Prior Art
Computer designers are continually attempting to make computers run faster. One way in which this may be accomplished is to make the computer process instructions faster. Typically, a computer processor handles the instructions of any process in sequential order, one after another. Thus, instruction one must be processed or at least begun before instruction two can start.
One way in which the speed of processing is increased is by pipelining instructions. Instead of running each instruction until it is completed and then commencing the next instruction, an instruction is divided into stages which are carried out by different portions of the processor. Then, the stages of sequential instructions are overlapped so that, in general, no portion of the processor lies idle while any particular stage of an instruction is being carried out. Optimally, the processors are designed to pipeline instructions so that each stage of each instruction may be handled in one clock period. The typical stages of a pipelined instruction include a stage in which an instruction is fetched from wherever it is stored, one in which it is decoded, a stage in which the instruction is executed, and a final stage in which the results of the execution stage are written back to storage for later use. The different portions of the processor carry out each of the stages in the pipeline on sequential instructions during each clock period. Thus, during a first clock period the prefetch portion of the processor fetches a first instruction from storage and aligns it so that is ready for decoding. During a second clock period the prefetch portion of the processor fetches the next instruction from storage and aligns it so that is ready for decoding. During the same second clock period, a decoder portion of the processor decodes the first instruction fetched. During a third clock period, the first instruction is executed, the second instruction is decoded, and a third instruction is fetched. By pipelining instructions, the overall speed of operation is significantly increased so that modern microprocessors typically execute one instruction every clock period.
The most prevalent design of personal computers at the present time is based on the 8086 8088, 80286 i386.TM., and i486.TM. microprocessors manufactured by Intel Corporation (hereinafter referred to as the Intel microprocessors). The Intel microprocessors utilize five stages of pipelining rather than the four stages outlined above. The stages include a prefetch stage, a first decode stage in which instructions are decoded, a second decode stage in which address of operands of the various instructions is calculated, an execution stage, and a write back stage.
Another way to increase the speed of microprocessors is to allow them to process more than one instruction at the same time. A superscaler processor is a processor which is capable of processing instruction through two separate processing channels at the same time. A new superscaler microprocessor which is able to operate with programs designed for the Intel microprocessors is disclosed in U.S. patent application Ser. No. 07/823,881, entitled Microprocessor With Apparatus For Parallel Execution of Instructions, E. Grochowski et al, filed Jan. 23, 1992, and assigned to the assignee of the present invention. The processor disclosed includes a pair of separate arithmetic and logic units (ALUs) which handle data in two separate channels simultaneously. The two channels of the processor derive data and instructions from the same data cache and utilize the same register files and stack.
Because both of the processing channels utilize the pipelining techniques of the previous Intel microprocessors, there are a number of occasions in which instructions in one or the other of the two channels make use of information being processed in an immediately preceding instruction. In such cases, the steps of the pipelining process require that the first of two sequential instructions be completed and its results stored before that information may be used by the next instruction. In such microprocessors, this would often required that the pipeline be stalled for one clock period until the completion of the write back stage of the first instruction.
There are similar occasions in which a stack pointer value is modified by a first instruction and the modified value is used by an instruction immediately following the instruction which modifies the pointer value. Such an operation would typically require that the pipeline be stalled until the stack pointer value from first instruction has been written back to the stack pointer register.
It would be useful to provide circuitry for obviating the need to stall the pipeline to provide for such situations.